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*参照元 [#n0e80b18] #backlinks *説明 [#s90d1903] -パス: [[linux-4.4.1/arch/arm64/mm/cache.S]] -FIXME: これは何？ --説明 --キャッシュの内容を破棄する --キャッシュの内容は残らないので、次に CPU から read したときキャッシュにヒットしない 原文 Invalidation means to clear it of data, by clearing the valid bit of one or more cache lines. The cache must always be invalidated after reset as its contents are undefined. This can also be viewed as a way of making changes in the memory domain outside the cache visible to the user of the cache. Cleaning means writing the contents of cache lines that are marked as dirty, out to the next level of cache, or to main memory, and clearing the dirty bits in the cache line. This makes the contents of the cache line with the next level of the cache or memory system. This is only applicable for data caches in which a write-back policy is used. This is also a way of making changes in the cache visible to the user of the outer memory domain, but is only available for data cache. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/BABJDBHI.html **引数 [#e2c51cde] -void *start -- -void *end -- **返り値 [#c5f9b510] -なし **参考 [#c5e970eb] *実装 [#jb052321] /* * __dma_inv_range(start, end) * - start - virtual start address of region * - end - virtual end address of region */ __dma_inv_range: dcache_line_size x2, x3 - --[[linux-4.4.1/dcache_line_size()]] sub x3, x2, #1 tst x1, x3 // end cache line aligned? bic x1, x1, x3 b.eq 1f dc civac, x1 // clean & invalidate D / U line 1: tst x0, x3 // start cache line aligned? bic x0, x0, x3 b.eq 2f dc civac, x0 // clean & invalidate D / U line b 3f 2: dc ivac, x0 // invalidate D / U line 3: add x0, x0, x2 cmp x0, x1 b.lo 2b dsb sy ret ENDPIPROC(__inval_cache_range) ENDPROC(__dma_inv_range) *コメント [#q71a420a]
